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Portable/Battery-Powered Equipment Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors
Portable/Battery-Powered Equipment Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors
40nm, Input Voltage Range of 2.1V to 2.9V, Fixed Output Voltage 1.1V
55nm, Single 1.2V power supply required, Fully integrated PLL-based clock generator including loop filter
40nm, Single 1.1V power supply is required, Fully integrated PLL-based clock generator including loop filter
40nm, Both 2.5V and 1.1V power supplies are required, Fully integrated PLL-based clock generator including loop filter
110nm, Fully integrated PLL-based clock generator including loop filter, Required voltage of 1.2/3.3v
180nm, 1.8V and 3.3V power supplies required, 3-Channel AFE with shared internal reference generator.
55/65nm, 12-bit 165 MHz ADC, Programmable Gain Amplifier
180nm, Power supplies of 1.8V and 5.0V are required, 3-Channel AFE with shared single reference block.
55nm, Channel 12-bit 165MSPS ADC, Single-ended Input with Fully differential Internal Processing
180nm, High speed current steering architecture, Dual channel matched analog outputs
180nm, Two Identical Channels, 10-bit Resolution
180nm, 3.3V analog and 1.2V digital supply, Differential output swing: -1.0V to +1.0V
55nm LL CMOS logic process without any mixed mode options.
65nm, Dual +1.2V/+3.3V power supplies required, Very small silicon area of 350um x850um with 1P7M layout structure.
55nm, Time interleaved architecture for excellent dual channel matching performance.
65nm, Time interleaved architecture for excellent dual channel matching performance.
130nm, 3.3V analog supply and 1.2V digital supply operation
55nm/65nm, 55nm GP CMOS logic process with low threshold voltage devices.