行业动态
流片信息
知识园地
IP目录
90nm, 10bit resolution pipelined analog-to-digital converter.
55nm LL CMOS logic process without any mixed mode options.
25nm, 1bit coarse and 7bit fine conversion architecture with folding and interpolation
180nm, Dual channel 10 bit A/D converters,Silterra 0.18G 1.8V/3.3V mixed mode CMOS technology
180nm, High speed pipeline architecture, 3.0V analog/digital supply, and 1.8V core digital supply
High speed pipeline architecture,1.8V analog supply and 1.8V digital supply operation
0.18um CMOS mixed mode process with MIM options.
55nm LL CMOS logic process without any mixed mode options.
55nm GP CMOS logic process with low threshold voltage devices.
40nm, Up to 300MHz Sample Rate, 10bit Digital Data Input
55nm, Up to 250MSPS sample rate, 250MHz system clock frequency
40nm, Differential Input Range Vp-p=2V, Dual-channel
55nm, Differential Input Range Vp-p=1V, Dual-channel
55nm, 100MSPS Throughput Rate, Output 10 bit Unsigned Codes
40nm, 2MHz Sample Rate, Output 12 bit signed code
40nm, 1MHz Sample Rate, Output 10 bit unsigned codes
12bit 60M pipeline ADC是一个高速、高精度、低功耗、双通道的ADC
具有增益可编程及自动校准功能的中频六阶复数滤波器,该滤波器为I/Q输入、差分输出
分数结构PLL,输出差分5.8GHz信号,可用作本振信号
应用于高品质音频处理领域的DAC